Xavier School of Computer Science and Engineering

Research & Publications


Research Summary


Dr Asuthosh Mishra
# Journal
2017, JOURNAL: Modified Frei-Chen Operator-Based Infrared and Visible Sensor Image Fusion for Real-Time Applications, IEEE

2015, JOURNAL: VLSI-Assisted Nonrigid Registration Using Modified Demons Algorithm, IEEE

Dr Goutam Mali
#Journal
2017, JOURNAL: Topology Management-Based Distributed Camera Actuation in Wireless Multimedia Sensor Networks, ACM

2016, JOURNAL: TRAST: Trust-Based Distributed Topology Management for Wireless Multimedia Sensor Networks, IEEE

2015, JOURNAL: Distributed topology management for wireless multimedia sensor networks: exploiting connectivity and cooperation, Wiley

Conference/Seminar
2010, Conference-Attended: Non-preemptive test scheduling for Network-on-Chip (NoC) based systems by reusing NoC as TAM, Venue: Kuala Lumpur, Malaysia

Dr Monalisa Mandal
#Journal
2017, JOURNAL: “Multiobjective PSO-based Rank Aggregation: Application in Gene Ranking from Microarray Data, Elsevier

2015, JOURNAL: A Comparative Study Among Various Statistical Tests Using Microarray Gene Expression Data, Bentham Science

2015, JOURNAL: Prediction of Protein Subcellular Localization by Incorporating Multiobjective PSO-based Feature Subset Selection into the General form of Chou’s PseAAC, Springer Berlin Heidelberg

2015, JOURNAL: A PSO-based Approach for Pathway MarkerIdentificationfromGene-ExpressionData, IEEE

2014, JOURNAL: A Graph-Theoretic Approach for Identifying Nonredundant and Relevant Gene Markers from Microarray Data Using Multiobjective Binary PSO, PLOS (Public Library of Science)

2014, JOURNAL: Identifying Non-redundant Gene Markers from Microarray Data: A Multiobjective Variable Length PSO-based Approach, IEEE, USA

2014, JOURNAL: A Novel PSO-based Graph-Theoretic Approach for Identifying Most Relevant and Non-redundant Gene Markers from Gene Expression Data, Taylor & Francis

Dr. Rakesh Prasad Badoni
#Journal
Rakesh P. Badoni, D.K. Gupta and Pallavi Mishra, “A new hybrid algorithm for university course timetabling problem using events based on groupings of students”, Computers & Industrial Engineering, 78, 2014, 12-25.

Pallavi Mishra, D.K. Gupta and Rakesh P. Badoni, “A new algorithm for enumerating all possible Sudoku squares”, Discrete Mathematics, Algorithms and Applications, 8(2), 2016, 1650026 (14 PAGES).

Rakesh P. Badoni and D.K. Gupta, “A graph edge colouring approach for school timetabling problems”, International Journal of Mathematics in Operational Research, 6(1), 2014, 123-138.

Rakesh P. Badoni, D.K. Gupta and Anil K. Lenka, “A new approach for university timetabling problems”, International Journal of Mathematics in Operational Research, 6(2), 2014, 236-257.

Rakesh P. Badoni and D.K. Gupta, “A hybrid algorithm for university course timetabling problem”, Innovative Systems Design and Engineering, 6(2), 2015, 60-66.

Rakesh P. Badoni and D.K. Gupta, “A new algorithm based on students groupings for university course timetabling problem”, In Proceeding of 2nd International Conference on Recent Advances in Engineering & Computational Sciences (RAECS-2015), 2015, IEEE.

Sukhjit Singh, D.K. Gupta, Rakesh P. Badoni, E. Martinez and Jose L. Hueso, “Local convergence of a parameter based iteration with Holder continuous derivative in Banach spaces”, Calcolo, 54(2), 2017, 527-539.

C.S. Vorugunti, B. Mishra, Rahul Amin, Rakesh P. Badoni, Mrudula Sarvabhatla and Dheerendra Mishra, “Improving security of lightweight authentication technique for heterogeneous wireless sensor networks”, Wireless Personal Communications, 95(3), 2017, 3141-3166.

S. Kumar, Rakesh P. Badoni and P.J. Mohan, “Application of MADM methods for selecting the best private institution for professional courses in Uttarakhand state, India”, Annals of Computer Science and Information Systems, 10, 2017, 229-233.

Dr. Rudra Mohan Tripathy
#Journal
2013, “Towards Combating Rumors in Social Networks: Models & Metrics”, Intelligent Data Analysis, special issue on Dynamic Networks and Knowledge Discovery. Vol. 17(1), pp 149-175, IOS Press.
#Conferences
2010, “A study of rumor control strategies on social networks.”, In CIKM ’10: Proceedings of 19th ACM International Conference on Information and Knowledge Management, pp 1817-1820, Toronto, Canada

2011, “Towards the use of Online Social Networks for Efficient Internet Content Distribution”, In ANTS ’11: Proceedings of 5th IEEE International Conference on Advance Networks and Telecommunication, pp 1-6, Bangalore, India

2013, “Spatio-Temporal and Events based Analysis of Topic Popularity in Twitter”, In CIKM ’13: Proceedings of the 22nd ACM International Conference on Information and Knowledge Management, pp 219-228

2013, “Temporal Analysis of User Behavior and Topic Evolution on Twitter”, In BDA ’13: Proceedings of the 2nd International Conference on Big Data Analytics, Lecture Notes in Computer Science Volume 8302, pp 22-36

2013, “Complex Network Characteristics and Performance in Cricket”, In BDA ’13: Proceedings of the 2nd International Conference on Big Data Analytics, Lecture Notes in Computer Science Volume 8302, pp 133-150, December 2013.

2014, “Theme Based Clustering of Tweets”, In CoDS ’14: Proceedings of the 1st IKDD Conference on Data Sciences, pp 1-5, March 2014.

Dr. Bhaskar Mondal
#Journal
2018: A chaotic permutation and diffusion based image encryption algorithm for secure communications", Multimedia Tools and Applications, Springer DOI: 10.1007/s11042-018-6214-z

2018, JOURNAL: A Secure Biometric Image Encryption Scheme using Chaos and Wavelet Transformations, Recent Patents on Engineering. Publisher: Bentham Science, doi: 10.2174/1872212111666170223165916

2018: Use of “A Light Weight Secure Image Encryption Scheme Based on Chaos & DNA Computing" for Encrypted Audio Watermarking", International Journal of Advanced Intelligence Paradigms, Publisher: InderScience.

2017: A Light Weight Secure Image Encryption Scheme Based on Chaos & DNA Computing", Journal of KSU - Computer and Information Sciences, Publisher: Elsevier.

2016: A Nobel Chaos based Secure Image Encryption Algorithm", International Journal of Applied Engineering Research (IJAER)
# Conferences
2017: A Secure Partial Encryption Scheme Based on Bit Plane Manipulation" 7th International Symposium on Embedded Computing and System Design (IEEE), National Institute of Technology Durgapur, Durgapur, India-713209, 18-20 December 2017. DOI: 10.1109/ISED.2017.8303925

2017: A Comparative study on Cryptographic Image Scrambling, Second International Conference on Research in Intelligent and Computing in Engineering (RICE'17) , Proc.: Annals of Computer Science and Information Systems (ISSN- 2300-5963), Institute of Technology.

2016: An investigative and Inclusive study of retail Enterprise Sales Centered on Online Analytical Processing", International Conference on Advanced Computing and Communication Technologies- 2016, RG Education Socity, Rohtak, INDIA

2016: Intelligent Classification of Lung & Oral Cancer through diverse data mining algorithms", 2016 IEEE International Conference on Micro-Electronics and Telecommunication Engineering, SRM University Delhi NCR Campus, Gopeshwar, Uttarakhand, India

2016: A Key Agreement Scheme for Smart Cards Using Biometrics", IEEE International Conference on Computing Communication and Automation (ICCCA2016), Galgotias University, Uttar Pradesh, India
# Book Chapter:
2018: Cryptographic Image Scrambling Techniques, Book: Cryptographic and Information Security Approaches for Images and Videos, Publisher: CRC Press, Taylor & Francis Group. (in Press)

Chandan Misra
#Journal
Stark: Fast and Scalable Strassens Matrix Multiplication using Apache Spark, ACM Transaction on Parallel Computing (TOPC), 2017. (Submitted) Chandan Misra, Sourangshu Bhattacharya and Soumya K. Ghosh.

SprIntMap: A System for Visualizing Interpolating Surface using Apache Spark, 5th International Conference on Advanced Computing, Networking, and Informatics (ICACNI), 2017, Goa, India.Chandan Misra, Sourangshu Bhattacharya and Soumya K. Ghosh.

SangeetLab: A New Framework for Expressing Digital Indic Music, New Interfaces for Musical Expressions (NIME), 2017, Copenhagen, Denmark. (Accepted) Chandan Misra, Anupam Basu and Baidurya Bhattacharya

Swaralipi: A Framework for Transcribing and Rendering Indic Music, TENOR, 2016, Cambridge, UK. Chandan Misra, Tuhin Chakraborty, Anupam Basu and Baidurya Bhattacharya

A Demonstration of GeomSMS: An SMS Framework for Sharing Geospatial Features, ACM SIGSPATIAL, 2014, Texas, USA. Chandan Misra, Arindam Dasgupta and Soumya K. Ghosh

A New Framework to Preserve Tagore Songs, World Digital Libraries, TERI Press, 2010. Chandan Misra, Baidurya Bhattacharya and Anupam Basu

A New Framework to Preserve Tagore Songs, ICDL, 2010, New Delhi, India. Chandan Misra, Baidurya Bhattacharya and Anupam Basu
# Patents:
A System and Method for Computerized/electronic Creation, Rendering and Playback of Indic and Non-Western Music Piece, Indian Patent, 140/KOL/2013. (Filed for Examination)

Chandan Misra, Baidurya Bhattacharya and Anupam Basu

A System and Method for Creating, Rendering Indic and Non-Staff Sheet Music on Electronic Media, Indian Patent, 141/KOL/2013. (Applied) Chandan Misra, Baidurya Bhattacharya and Anupam Basu

Implementation of Meend or Musical Ornament in Indic Music System Using MIDI in Electronic Device, Indian Patent, 142/KOL/2013. (Applied) Chandan Misra, Baidurya Bhattacharya and Anupam Basu

A Method and System for Implementing and Transmitting Indic Microtones into Electronic Transmittable Format, Indian Patent, 143/KOL/2013. (Applied) Chandan Misra, Baidurya Bhattacharya and Anupam Basu

A Method for Electronically Transcribing, Storing Indic Music Information and Transferring Stored Musical Data Electronically, Indian Patent, 144/KOL/2013. (Filed for Examination) Chandan Misra, Baidurya Bhattacharya and Anupam Basu
Research Projects:
SprIntMap: A SYSTEM FOR VISUALIZING INTERPOLATING SURFACE USING APACHE SPARK Big Data, Apache Spark, MapReduce, HDFS - IIT Kharagpur; Oct. 2015 - Jan. 2016

Developed a web application which allows users to fetch and process large climate datasets from National Oceanic and Atmospheric Administration (NOAA) and visualize the resulting interpolated surfaces of large areas in reasonable time.

KEY: KNOWLEDGE EMPOWERS YOU - Text Mining, Contextual S earch, Corporate Kno w led ge - TCS Innovation Lab, Hyderabad; Jun. 2016 - Aug. 2016 Built a prototype for contextual knowledge delivery to TCS employees that provides extended search capability and taxonomy tree of corporate knowledge repositories.

SYSTEM FOR ENCODING, RENDERING AND PLAYING BACK INDIC MUSIC SHEETS - Computer Music, Design and Prototyping, HCI, Art - IIT Kharagpur; Mar 2009 - Sep. 2012

Developed first of its kind music notation software for creating, saving, and performing Indic music sheet in computer.

MATHEMATICAL MODEL FOR DEFINING THE ARCHITECTURE OF INDIC MUSIC SHEET Computer Music, Mathematical Model, H CI, Art - IIT Kharagpur; Mar 2009 - Sep. 2012

Built a 2D matrix model for creating music sheets in Indic notation systems and language scripts.


Priyadarsan Patra

 

Prof. Priyadarsan Patra (updated July 2019)

  1. Mondal B and Patra P (2019), “A Framework for Personalized Online Learning based on ML”, In 25th IAJBS World Forum and Inaugural CJBE South Asia Regional Chapter Meeting. Vol. 25(1), pp. 1.
  2. Monalisa Mandal, S. K. Sahoo and P. Patra, “In Silico Ranking of Phenolics for Therapeutic Effectiveness on Cancer Stem Cell”, 2019. [to be published]
  3. Mathew D, Jose BA and Patra P (2019), "Performance Analysis of Microkernel Based Virtualization Techniques on Embedded Systems", Journal of Low Power Electronics. Vol. 15(2), pp. 273-281. American Scientific Publishers.[BibTeX] [URL]
  4. Mathew J, Jose BA and Patra P (2019), "Selected Articles from the ISED 2018 Conference", Journal of Low Power Electronics. Vol. 15(2), pp. 160-161. American Scientific Publishers.[BibTeX] [URL]
  5. Mondal B and Patra P (2019), "A Framework for Personalized Online Learning based on ML", In 25th IAJBS World Forum and Inaugural CJBE South Asia Regional Chapter Meeting. Vol. 25(1), pp. 1.[BibTeX]
  6. Patra P (2019), "The Landscape of AI and implications to Policy and Future Sustainability", The Journal of Management for Global Sustainability., In (selections from 25th IAJBS World Forum). Vol. 25(1), pp. 4.[BibTeX]
  7. P. Patra, et al (2018). “Debug Infrastructure for System-on-chips”, IEEE SVDTC White Paper on Debug, (Role: Founding General Chair and Co-Author). IEEE System Validation & Debug Technology Committee. [URL]
  8. P. Patra, et al (2017). “The Future of SoC System Validation & Debug… and Why You Should Care!”  International Design Automation Conference, Tutorial Track. IEEE 2017. [URL]
  9. J. Obedowski, P. Patra, et al (2017). “Co-Validation Initiatives within DCG SD”. Best of Published Papers Award. Intel Design, Test and Technology Conference (DTTC 2017)
  10. Mathew J, Rahaman H, Patra P and Pradhan DK (2017), "Selected Articles from the IEEE ISED 2016 Conference", J. Low Power Electronics. Vol. 13(4), pp. 605-606.[BibTeX] [DOI] [URL]
  11. P. Patra (2015), “Advances and Convergence in the notions of Compute, Communication, and Power.” PCTIC (2015 IEEE conf. on Power, Communication and Information Technology). Keynote. [URL]
  12. J. Obedowski, P. Patra, et al (Team presentation/paper), PARTI: Silicon Validation and Software Engineering Co-validation System. Intel 2017
  13. P. Patra (2015), “Challenges and opportunity in High-volume Manufacturing Test: Cost, Throughput, Quality & Complexity”. Birds of a Feather Invited Lecture, Intel Design and Test Technology Conf., 2015
  14. Irshad Ansar, P. Patra, et al, “An Ingenious IUNIT IP Test to FC SBFT Conversion Methodology to Address IPfication and Test Content Reusability Challenges”, Intel PSLE conf. 2015.
  15. Patra P and Prudvi C (2015), "Fabrics on Die: Where Function, Debug and Test Meet", In Proceedings of the 9th International Symposium on Networks-on-Chip, NOCS 2015, Vancouver, BC, Canada, September 28-30, 2015. , pp. 4:1-4:3.[BibTeX] [DOI] [URL]
  16. Mathew J, Rahaman H, Patra P and Pradhan DK (2015), "Selected Articles from the IEEE ISED 2014 Conference", Journal of Low Power Electronics. Vol. 11(3), pp. 373-374. [DOI] [URL]
  17. Mathew J, Vinod AP and Patra P (2014), "Selected Articles from the IEEE ISED 2013 Conference", J. Low Power Electronics. Vol. 10(3), pp. 399-400.[BibTeX] [DOI] [URL]
  18. Sarkar A, Mandal JK and Patra P (2013), "Double Layer Perceptron Synchronized Computational Intelligence Guided Fractal Triangle Based Cryptographic Technique for Secured Communication (DLPFT)", In 2013 International Symposium on Electronic System Design, Singapore, December 10-12, 2013. , pp. 191-195.[BibTeX] [DOI] [URL]
  19. Basu K, Mishra P, Patra P, Nahir A and Adir A (2013), "Dynamic Selection of Trace Signals for Post-Silicon Debug", In 14th International Workshop on Microprocessor Test and Verification, MTV 2013, Austin, TX, USA, December 11-13, 2013. , pp. 62-67.[BibTeX] [DOI] [URL]
  20. Basu K, Mishra P and Patra P (2013), "Observability-aware Directed Test Generation for Soft Errors and Crosstalk Faults", In 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, Pune, India, January 5-10, 2013. , pp. 291-296.[BibTeX] [DOI] [URL]
  21. Mathew J and Patra P (2013), "Selected Articles from the IEEE ISED 2012 Conference", J. Low Power Electronics. Vol. 9(3), pp. 302.[BibTeX] [DOI] [URL]
  22. Basu K, Mishra P and Patra P (2012), "Constrained signal selection for post-silicon validation", In 2012 IEEE International High Level Design Validation and Test Workshop, HLDVT 2012, Huntington Beach, CA, USA, November 9-10, 2012. , pp. 71-75.[BibTeX] [DOI] [URL]
  23. K. Jones, J. Baudrexl, V. Liew, P. Patra, B. Mathur (2012), “Closed-Chassis DFx Access with Embedded DFx Interface (ExI)”, Intel Design and Test Technology Conference (DTTC Intel) 2012.
  24. Mathew J, Pradhan D and Patra P (2012), "Eco-friendly Computing and Communication Systems" Springer, ISBN: 978-3-642-32111-5.[BibTeX] [URL]
  25. Garitselov O, Mohanty SP, Kougianos E and Patra P (2011), "Bee Colony Inspired Metamodeling Based Fast Optimization of a Nano-CMOS PLL", In International Symposium on Electronic System Design, ISED 2011, Kochi, Kerala, India, December 19-21, 2011. , pp. 6-11.[BibTeX] [DOI] [URL]
  26. P. Patra and Rolando Santoyo (2011), “A Perspective on Pre-silicon Validation of the VCU”, Intel Design and Test Technology Conference (DTTC Intel) 2011
  27. Basu K, Mishra P and Patra P (2011), "Efficient combination of trace and scan signals for post silicon validation and debug", In 2011 IEEE International Test Conference, ITC 2011, Anaheim, CA, USA, September 20-22, 2011. , pp. 1-8.[BibTeX] [DOI] [URL]
  28. E. Kougianos, S. Mohanty and P. Patra (2010). "Digital Nano-CMOS VLSI Design Courses in Electrical and Computer Engineering Through Open-Source Tools", NSF-sponsored, invited workshop. 2010
  29. Garitselov O, Mohanty SP, Kougianos E and Patra P (2010), "Nano-cmos mixed-signal circuit metamodeling techniques: A comparative study", In 2010 International Symposium on Electronic System Design. , pp. 191-196.[BibTeX] [URL]
  30. Ghai D, Mohanty SP, Kougianos E and Patra P (2009), "A PVT aware accurate statistical logic library for high- metal-gate nano-CMOS", In 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA. , pp. 47-54.[BibTeX] [DOI] [URL]
  31. Priyadarsan Patra, et al. (2010), “Validation Control Unit”, Intel Design, Test and Technology Conference (DTTC), 2010 (Best Paper nominee)
  32. Mohanty SP, Ghai D, Kougianos E and Patra P (2009), "A combined packet classifier and scheduler towards net-centric multimedia processor design", In 2009 Digest of Technical Papers International Conference on Consumer Electronics. , pp. 1-2.[BibTeX] [URL]
  33. Priyadarsan Patra, et al. (2009), “Enabling Probeless REPLAY & DEBUG for Westmere EX”, Intel Design, Test and Technology Conference (DTTC), 2009
  34. Priyadarsan Patra CP (2008), "IP Session 6C: Post-Silicon Validation Challenges of Highly Integrated Processors: in Current Practices and New Challenges for the Testing Community", In 26th IEEE VLSI Test Symposium (vts 2008)., April, 2008. , pp. 199-199.[BibTeX] [DOI]
  35. Chen K, Malik S and Patra P (2008), "Runtime validation of memory ordering using constraint graph checking", In 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 16-20 February 2008, Salt Lake City, UT, USA. , pp. 415-426.[BibTeX] [DOI] [URL]
  36. Chen K, Malik S and Patra P (2008), "Runtime Validation of Transactional Memory Systems", In 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA. , pp. 750-756.[BibTeX] [DOI] [URL]
  37. Li B, Peh L and Patra P (2008), "Impact of Process and Temperature Variations on Network-on-Chip Design Exploration", In Second International Symposium on Networks-on-Chips, NOCS 2008, 5-6 April 2008, Newcastle University, UK. Proceedings. , pp. 117-126.[BibTeX] [DOI] [URL]
  38. Mohanty SP, Ranganathan N, Kougianos E and Patra P (2008), "Power Modeling and Estimation at Transistor and Logic Gate Levels", In Low-Power High-Level Synthesis for Nanoscale CMOS Circuits. , pp. 47-79. Springer, Boston, MA.[BibTeX]
  39. Mohanty SP, Ranganathan N, Kougianos E and Patra P (2008), "Architectural Power Modeling and Estimation", In Low-Power High-Level Synthesis for Nanoscale CMOS Circuits. , pp. 81-130. Springer, Boston, MA.[BibTeX]
  40. Mohanty SP, Ranganathan N, Kougianos E and Patra P (2008), "Energy or Average Power Reduction", In Low-Power High-Level Synthesis for Nanoscale CMOS Circuits. , pp. 163-200. Springer, Boston, MA.[BibTeX]
  41. Mohanty SP, Ranganathan N, Kougianos E and Patra P (2008), "High-Level Synthesis Fundamentals", In Low-Power High-Level Synthesis for Nanoscale CMOS Circuits. , pp. 5-46. Springer, Boston, MA.[BibTeX]
  42. Mohanty SP, Ranganathan N, Kougianos E and Patra P (2008), "Leakage Power Reduction", In Low-Power High-Level Synthesis for Nanoscale CMOS Circuits. , pp. 261-276. Springer, Boston, MA.[BibTeX] [URL]
  43. Mohanty SP, Ranganathan N, Kougianos E and Patra P (2008), "Low-power High-level Synthesis for Nanoscale CMOS Circuits" Springer, ISBN: 978-0-387-76474-0.[BibTeX] [URL]
  44. Mohanty SP, Ranganathan N, Kougianos E and Patra P (2008), "Peak Power Reduction", In Low-Power High-Level Synthesis for Nanoscale CMOS Circuits. , pp. 201-224. Springer, Boston, MA.[BibTeX]
  45. Mohanty SP, Ranganathan N, Kougianos E and Patra P (2008), "Power reduction fundamentals", In Low-Power High-Level Synthesis for Nanoscale CMOS Circuits. , pp. 131-162. Springer, Boston, MA.[BibTeX]
  46. Mohanty SP, Ranganathan N, Kougianos E and Patra P (2008), "Transient Power Reduction", In Low-Power High-Level Synthesis for Nanoscale CMOS Circuits. , pp. 225-259. Springer, Boston, MA.[BibTeX]
  47. Patra P (2007), "On the cusp of a validation wall", IEEE Design & Test of Computers. Vol. 24(2), pp. 193-196.[BibTeX] [DOI] [URL]
  48. Mohanty S, Kougianos E, Ghai D and Patra P (2007), "Interdependency study of process and design parameter scaling for power optimization of nano-cmos circuits under process variation", In Proceedings of the 16th ACM/IEEE International Workshop on Logic and Synthesis (IWLS-2007). , pp. 207-213.[BibTeX] [URL]
  49. Pan M, Chu C and Patra P (2007), "A novel performance-driven topology design algorithm", In Proceedings of the 2007 Asia and South Pacific Design Automation Conference. , pp. 244-249.[BibTeX] [URL]
  50. Priyadarsan Patra. Formal Correctness of a mesh-based clock deskew scheme. (Tech Report, Intel Corp.) 2004.
  51. Büyüksahin KM, Patra P and Najm FN (2003), "ESTIMA: an architectural-level power estimator for multi-ported pipelined register files", In Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003. , pp. 294-297.[BibTeX] [DOI] [URL]
  52. Dike CE, Kurd NA, Patra P and Barkatullah J (2003), "A design for digital, dynamic clock deskew", In 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No. 03CH37408). , pp. 21-24.[BibTeX] [URL]
  53. Chappell B, Wang X, Patra P, Saxena P, Vendrell J, Gupta S, Varadarajan S, Gomes W, Hussain S, Krishnamurthy H and others (2002), "A system-level solution to domino synthesis with 2 GHz application", In Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors. , pp. 164-171.[BibTeX] [URL]
  54. Patra P, Narayanan U and Kim T (2001), "Phase assignment for synthesis of low-power domino circuits", Electronics Letters. Vol. 37(13), pp. 814-816. IET Digital Library.[BibTeX] [URL]
  55. Ketkar M, Sapatnekar SS and Patra P (2000), "Convexity-based optimization for power-delay tradeoff using transistor sizing", In Proc. ACM/IEEE Int. Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU'00). , pp. 52-57.[BibTeX] [URL]
  56. Patra P (2000), "A perspective on power issues in Ultra DSM circuits", In Invited talk/abstract presented at Int’l Conference on Information Technology, CIT. Vol. 2000[BibTeX]
  57. Patra P and Narayanan U (1999), "Automated phase assignment for the synthesis of low power domino circuits", In Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361). , pp. 379-384.[BibTeX] [URL]
  58. Patra P, Polonsky S and Fussell DS (1997), "Delay Insensitive Logic for RSFQ Superconductor Technology", In 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 7-10 April 1997, Eindhoven, The Netherlands. , pp. 42-53.[BibTeX] [DOI] [URL]
  59. Patra P and Fussell DS (1996), "Efficient Delay-Insensitive RSFQ Circuits", In 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings. , pp. 413-418.[BibTeX] [DOI] [URL]
  60. Patra P and Fussell DS (1996), "A framework for conservative and delay-insensitive computing", In Proceedings of 4th Workshop on Physics and Computation(PhysComp’96).[BibTeX] [URL]
  61. Patra P and Fussell DS (1995), "Power-efficient delay-insensitive codes for data transmission", In 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA. Vol. 1, pp. 316-323.[BibTeX] [DOI] [URL]
  62. Patra P and Fussell DS (1995), "Fully asynchronous, robust, high-throughput arithmetic structures", In 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India. , pp. 141-145.[BibTeX] [DOI] [URL]
  63. Patra P (1995), "Approaches to design of circuits for low-power computation". Thesis at: University of Texas at Austin.[BibTeX] [URL]
  64. Patra P and Fussell DS (1995), "Asymptotically zero power in reversible sequential machines", In In 1985 Chapel Hill Conference on VLSI.[BibTeX] [URL]
  65. Patra P and Fussell DS (1994), "Efficient building blocks for delay insensitive circuits", In Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, ASYNC 1994, Salt Lake City, UT, USA, November 3-5, 1994. , pp. 196-205.[BibTeX] [DOI] [URL]
  66. Patra P and Fussell DS (1994), "Optimization of delay-insensitive circuits -- a case study". Thesis at: Citeseer.[BibTeX] [URL]
  67. Patra P and Fussell DS (1993), "Building-blocks for designing DI circuits" University of Texas at Austin, Department of Computer Sciences.[BibTeX] [URL]
  68. Josephs MB and Patra P (1992), "An asynchronous bitserial adder and its delay-insensitive decomposition". Thesis at: Technical report, Oxford University Computing Lab., Oxford, 1992 ….[BibTeX]
  69. Hsu T-s, Patra P and Yang H (1990), "A Partial Report on Parallel Graph Algorithms (EE 382L term project)". Thesis at: Technical report, University of Texas at Austin, USA.[BibTeX]